Udemy – SystemVerilog for Verification Part 2: Projects 2022-9 – Download

Explanation

Verilog System for Verification Part 2: Industrial VLSI projects can be divided into two branches, namely, RTL design and RTL verification. Verilog and VHDL are still popular choices for most design engineers working in RTL design. Functional verification can also be done in Hardware Description Language, but Hardware Description Language has limited ability to perform code coverage analysis, corner case testing, and so on, and writing TB code may not be possible. complex systems sometimes. SystemVerilog has become the first choice of verification engineers to perform verification of complex RTL’s. SystemVerilog-oriented capabilities such as inheritance, polymorphism, and randomization allow users to find critical bugs with minimal effort.

Any complex system of FPGAs is built with the help of many subsystems. These subsystems can be simple sequential modules / simple integrated modules / RTL data communication protocol / RTL protocol bus. Once we understand the strategies for verifying common subsystems, you can easily perform verification of any complex system with the same logic. Our objective in the course will be to build logic with the help of the basics discussed in the first part of the course to ensure the realization of these common subsystems. We start our course by implementing the realization of data flipflops and FIFOs, then we continue with the realization of common data communication protocols, such as, SPI, UART, and I2C. Finally, we will perform verification of bus protocols, such as, ABP, AHB, AXI, and Wishbone protocol.