Explanation
This course covers advanced topics in high-level design flow (HLS). The goal of the course is to define, debug and implement logic circuits in FPGAs using only C/C++ language without any help from HDLs (eg, VHDL or Verilog). HLS is recently used by several industry leaders (such as Nvidia and Google) to design their hardware and software tools. HLS design flow is the future of hardware design. It is quickly becoming a must-have skill for any hardware or software engineer interested in utilizing FPGAs for their exceptional performance and low power consumption. This course is the first to describe advanced HLS design flow topics. It uses Xilinx HLS software and hardware tools to demonstrate examples and real-world applications.
Throughout the course, you will follow several examples that illustrate HLS concepts and techniques. The course contains a large number of questions and exercises to practice and learn the proposed methods and procedures. This course is the third in a series of courses on HLS in hardware component design and acceleration algorithms targeting FPGA. While this course focuses on multi-circuit design, advanced design, and optimization techniques for HLS, other courses in the series explain how to use single-circuit design techniques to develop integrated and sequential logic circuits for HLS.
What will you learn?
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Using a multi-circuit design flow to develop HLS sequential circuits.
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Implementation of flow communication and computing within HLS
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Using FIFO as a connection mechanism between connected modules
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Learning how to use array variables in HLS code
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Networking and AND HLS IP to BRAMs in Vivado project
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Working with HLS indicators
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Working with AXI protocol in HLS
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HLS loop pipeline optimization
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HLS recording reformatting
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HLS extended loop optimization
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Retrospective reformulation of HLS
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Working with the HLS-Stream library for HLS
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HLS handshake and interaction protocol
Who is this course for?
- hardware engineers
- Software engineers interested in FPGAs
- Teachers, researchers, and professors who want to use FPGA-based HLS for lessons, courses or research.
- Digital Logic Enthusiasm
Advanced FPGA Integration Guide, Part 3 – Advanced
- Publisher: Udemy
- Teacher: Mohamed Hosseinbady
- Language : English
- Level: Medium
- Number of courses: 58
- Duration : 7 hours and 33 minutes
High Level FPGA Integration Content, Part 3 – Advanced
Requirements
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Understand the basic concepts of C/C++ coding
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Understand the basic concepts of logical operators (eg, AND, OR, FREE, SHIFT)
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“FPGA Advanced, Part 1 – Integrated Circuits” Udemy course
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“FPGA Advanced, Part 2 – Serial Circuits” Udemy course
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Xilinx Vitis-HLS and Vivado (download Vivado ML Edition or Vivado Design Suite – HLx Editions for Windows or Linux)
Pictures
Sample Clip
Installation Guide
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Quality: 720p
Download Links
Password file: free download software
file size
3.52 GB