Udemy – Advanced FPGA Integration, Part 2 – Serial Circuits 2022-1 – Download

Explanation

This course is an introduction to high level integrator (HLS) sequential circuit design. The goal of the course is to define, debug and implement sequential logic circuits in FPGAs using only C/C++ language without any help from HDLs (eg, VHDL or Verilog). It uses Xilinx HLS software and hardware tools to demonstrate examples and real-world applications. The course mainly uses the Xilinx Vitis-HLS tool to explain, visualize and process high-level design descriptions equivalent to HDL code. The course also explains how to use Vivado’s Integrated Logic Analyzer (ILA) IP to perform real-time debugging of the Basys3 board.

This course is the first of its kind to build HLS design flow and skills along with digital logic circuit concepts from scratch. Throughout the course, you will follow several examples that illustrate HLS concepts and techniques. The course contains many questions and exercises for you to practice and learn the proposed methods and procedures. In addition, the course uses three interesting projects to combine all the concepts explained to design real circuits and hardware controllers. This course is the second in a series of courses on HLS in hardware component design and acceleration algorithms targeting FPGA. While this course focuses on sequential circuits, the first course explains how to define integrated circuits in HLS. Other courses in the series will explain how to use HLS to design advanced logic circuits, algorithm acceleration, and CPU+FPGA integration for various systems.

What will you learn?

Designing sequential logic circuits in C/C++ language using HLS method
Understanding the basic concepts of High Level Synthesis (HLS)
Using HLS concepts in the design of sequential logic circuits
HLS design flow for FPGAs
Working with Xilinx Vitis-HLS and Vivado design suite Toolsets
How to generate RTL hardware IPs using Vitis-HLS
Writing C-testbench in HLS
Implementation of three exciting projects at HLS

Who is this course for?

hardware engineers
Software engineers interested in FPGA
Teachers, researchers, professors who want to use FPGA-based HLS for lessons, courses or research
Digital Logic Enthusiasm