Explanation
ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog, which focuses on verification of coding style and naming conventions, RTL and output-combination mismatch, optimal balance, description of the correct FSM, avoidance of problems in additional design stages, timing and reconfiguration of tree issues, CDC, RDC, DFT, and code portability and reuse. The solution performs continuous analysis based on RTL and SDC ™ source files that reveal critical design issues early in the design cycle, thereby significantly reducing design markup time. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues from spreading to lower stages of the design flow and reduces the number of iterations needed to complete the design.
ALINT-PRO presents a well-designed, intuitive interface, which provides features for efficient design analysis including RTL schematic viewer, FSM viewer, timer and replay, schematics viewer, detail viewer, Violation viewer, and special tools like CDC viewer, RDC viewer, and CDC schematics for clock and reconfiguration domain cut analysis.
Features of Aldec ALINT-PRO 2021.09 x64
- Clock and Reset Network Analysis
- Avoiding post-RTL and post-Synthesis simulation simulations
- Verifying the accuracy of FSM descriptions
- Graphical exploration of generated FSMs and identified FSM issues
- Code Capture and Reuse
- Extensive CDC and RDC checks with the ALDEC_CDC rule plug-in
- Advanced CDC and RDC Debugging Environment
- A structured viewer
- Checking the DFT
- SDC™ support
- Design Challenges for Expanding IP Descriptions
- Basic and batch running modes
System required
- Windows® 10/8.1/8/7 (64-Bit)
Pictures
Installation Guide
Read the Readme.txt file in the Crack folder
Download Links
Download Aldec ALINT-PRO 2021.09 x64
Password file: free download software
file size
913 MB