Explanation
This course is a basic introduction to the high level design (HLS) flow. The goal of the course is to define, debug and implement integrated logic circuits in FPGAs using only C/C++ language without any help from HDLs (eg, VHDL or Verilog). HLS is recently used by several industry leaders (such as Nvidia and Google) to design their hardware and software tools. HLS design flow is the future of hardware design, which is quickly becoming a must-have skill for any hardware or software engineer interested in exploiting FPGAs for their exceptional performance and low power consumption.
It uses Xilinx HLS software and hardware tools to demonstrate examples and real-world applications. This course is the first to build HLS design flow and skills along with digital logic circuit concepts from scratch. Throughout the course, you will follow several examples that illustrate HLS concepts and techniques. The course contains many questions and exercises for you to practice and learn the proposed methods and procedures. This course is the first in a series of courses on HLS in hardware component design and acceleration algorithms targeting FPGA. While this course focuses on integrated circuits. Other courses in the series will explain how to use HLS to design sequential logic circuits, algorithm acceleration, and CPU+FPGA integration for different systems.
What will you learn?
- Design of integrated logic circuits in C/C++ language using HLS method
- Understanding the basic concepts of High Level Synthesis (HLS)
- Using HLS concepts in the design of integrated logic circuits
- HLS design flow for FPGAs
- Working with Xilinx Vitis-HLS and Vivado suite Toolsets
- How to generate RTL hardware IPs using Vitis-HLS
- Writing C-testbench in HLS
- Implementation of two interesting projects at HLS
Who is this course for?
- hardware engineers
- Software engineers interested in FPGAs
- Teachers, researchers, professors who want to use FPGA-based HLS for lessons, courses or research
- Digital Logic Enthusiasm
FPGA Advanced Integration Guide, Part 1—Integration Packages
- Publisher: Udemy
- Teacher: Mohamed Hosseinbady
- Language : English
- Level: Beginner
- Number of courses: 110
- Duration: 7 hours and 47 minutes
FPGA High-Level Integration Content, Part 1—Integration Packages
Requirements
- Understand the basic concepts of C/C++ coding
- Understand the basic concepts of logical operators (eg, AND, OR, FREE, SHIFT)
- BASYS3 evaluation panel
- Xilinx Vitis-HLS and Vivado (download Vivado ML Edition, or Vivado Design Suite – HLx Editions for Windows or Linux)
Pictures
Sample Clip
Installation Guide
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Subtitle : English
Quality: 720p
Download Links
Password file: free download software
file size
6.82 GB